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Qsys System Integration Tool
The Qsys system integration tool saves significant time and effort in the FPGA design process by
automatically generating interconnect logic to connect intellectual property (IP) functions and
subsystems. Qsys is powered by a new FPGA-optimized network-on-a-chip (NoC) technology,
delivering higher performance, improved design reuse, and faster verification.
? High-performance Qsys interconnect based on the NoC architecture and automatic pipelining
delivers up to 2X higher performance
? Hierarchical design flow enables scalable designs, supports team-based design, and maximizes
design reuse
? Higher flexibility with support for mixing different industry-standard interfaces, such as the AMBA?
AXI?, AMBA APB TM , AMBA AHB TM , and Avalon? interfaces
? IP management capabilities enable designs and systems to appear as an IP for easier reuse
? Faster board bring-up with a system-level debug approach using address-based transactions and
System Console
Qsys – Altera’s System Integration Tool
High-
Performance
Interconnect
Hierarchy
Industry-Standard
Interface
IP Management
Real-Time
System Debug
Quartus II Design Software
?
2013
?
www.altera.com
5
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